1. Field of the Invention
The present invention relates generally to a through silicon via and a process thereof, and more specifically to a through silicon via and a process thereof that forms a conductive filling material in a hole before a photoresist is formed.
2. Description of the Prior Art
The through-silicon via technique is a quite novel semiconductor technique. The through-silicon via technique mainly consists in solving the problem of the electrical interconnection of chips and belongs to a new 3D packing field. The hot through-silicon via technique creates products which meet the market trends of “light, thin, short and small” better thanks to 3D stacking through the through-silicon via, so as to provide the micro electronic mechanic system (MEMS), the photoelectronic and electronic elements with packing techniques of a wafer-level package.
The through-silicon via technique drills holes in the wafer by etching or by laser then fills the holes with conductive materials, such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. At last, the wafer or the dice is thinned to be stacked or bonded together to be a 3D stack IC. In such a way, the wire bonding procedure may be omitted. Using etching or laser processes to form conductive vias not only avoids the wire bonding but also shrinks the occupied area on the circuit board and the overall volume for packing.
When comparing the inner connection distance of the package by the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, with the conventional stack package of wire bonding type, the 3D stack IC shows much shorter inner connection distances, so the 3D stack IC performs better in many ways, such as providing a smaller electrical resistance, faster transmissions, lower noise and better performances. The advantages of the shorter inner connection distance of the through-silicon via technique are much more outstanding, especially for the CPU, the flash memories and the memory cards. In addition, the package size of the 3D stack IC equals the size of the dice, so the through-silicon via technique is more valuable in the portable electronic devices.
However, as the miniaturization of semiconductor components increase, the depth/width aspect ratio of a through silicon via in these semiconductor components become higher, leading to the difficulties for forming the through silicon via.